Process and Device Performance of 1-μm-Channel N-Well CMOS Using Deep-Trench Isolation Technology

CMOS has become an attractive VLSI technology because of its low power dissipation, large noise immunity, patternlayout ease for gate-array logic circuits, and compatibility with analog circuits. In order to make high-speed/high-density CMOSVLSIs, the device geometry has had to be continuously scaled down. However, scaled-down bulk-CMOS has susceptibility to latch up and poor device-to-device isolation because of the narrow space between n- and p-channel devices and the shallow well depth.