• DocumentCode
    472887
  • Title

    High Performance 1.0 μm N-Well CMOS/Bipolar Technology

  • Author

    Momose, H. ; Shibata, H. ; Mizutani, Y. ; Kanzaki, K. ; Kohyama, S.

  • Author_Institution
    Semiconductor Device Engineering Laboratory Toshiba Corporation Kawasaki Japan
  • fYear
    1983
  • fDate
    13-15 Sept. 1983
  • Firstpage
    40
  • Lastpage
    41
  • Abstract
    For achieving high performance VLSI´s in logic and memory applications, CMOS becomes the dominant technology due to its very low power capability. As a 1.0 pμm level CMOS technology, it is quite attractive to develop a bipolar compatible process for combining high speed digital circuits with high performance analog circuits on the same chip.
  • Keywords
    Bipolar transistors; Boron; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS process; CMOS technology; MOS devices; Power supplies; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 1983. Digest of Technical Papers. Symposium on
  • Conference_Location
    Maui, HI, USA
  • Print_ISBN
    4-930813-05-0
  • Type

    conf

  • Filename
    4480627
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=472887