Title :
High Performance 1.0 μm N-Well CMOS/Bipolar Technology
Author :
Momose, H. ; Shibata, H. ; Mizutani, Y. ; Kanzaki, K. ; Kohyama, S.
Author_Institution :
Semiconductor Device Engineering Laboratory Toshiba Corporation Kawasaki Japan
Abstract :
For achieving high performance VLSI´s in logic and memory applications, CMOS becomes the dominant technology due to its very low power capability. As a 1.0 pμm level CMOS technology, it is quite attractive to develop a bipolar compatible process for combining high speed digital circuits with high performance analog circuits on the same chip.
Keywords :
Bipolar transistors; Boron; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS process; CMOS technology; MOS devices; Power supplies; Very large scale integration; Voltage;
Conference_Titel :
VLSI Technology, 1983. Digest of Technical Papers. Symposium on
Conference_Location :
Maui, HI, USA
Print_ISBN :
4-930813-05-0
