Back and Side Channel Leakage in SOI CMOS

Source to drain leakage currents, flowing along the back and sides of the silicon islands, have been a problem in SOI technology from the earliest days of silicon on sapphire. These are particularly important in CMOS where they dominate the standby power and, with the advent of VLSI, they have become a major design consideration. A wide range of N and P channel devices and CMOS circuits has been made on a wide variety of SOI substrates including silicon on sapphire, laser recrystallised polysilicon, oxygen implanted silicon and strip heater recrystallised polysilicon as well as twin tub and conventional bulk CMOS processes. The emphasis has been on oxygen implanted material with various doses and energies, both with and without epitaxy and on strip heater recrystallised polysilicon. A standard CMOS test mask was used together with a fairly conventional CMOS process modified by using the active area mask to define the silicon islands. Junctions were implanted boron and arsenic with a junction depth (on the bulk, silicon controls) of 0.3¿m and 0.2¿m respectively. The gate oxide was 400Å thick with a phosohorous doped gate to maintain the closest compatibility with the bulk silicon controls.