Title :
Latch-Up Elimination in High Density CMOS
Author_Institution :
Hughes Research Laboratories 3011 Malibu Canyon Road Malibu, CA 90265
Keywords :
Annealing; CMOS process; CMOS technology; Circuits; Doping; FETs; Furnaces; Implants; Laboratories; Very large scale integration;
Conference_Titel :
VLSI Technology, 1983. Digest of Technical Papers. Symposium on
Conference_Location :
Maui, HI, USA
Print_ISBN :
4-930813-05-0
