A New EEPROM Cell with Dual Control Gate Structure

Author

Wada, M. ; Hieda, K. ; Shibata, T. ; Iizuka, H.

Author_Institution

Integrated Circuits Laboratory Toshiba Corporation, Kawasaki, Japan

fYear

1983

fDate

13-15 Sept. 1983

Firstpage

114

Lastpage

115

Keywords

Capacitance; Degradation; EPROM; Electrons; Laboratories; Nonvolatile memory; Testing; Threshold voltage; Tunneling; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1983. Digest of Technical Papers. Symposium on

Conference_Location

Maui, HI, USA

Print_ISBN

4-930813-05-0

Type

Filename

4480663

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