A 2 μm Stacked CMOS 64K SRAM

Author

Shah, A.H. ; Hite, L.R. ; Shetti, S. S Mahant ; Chatterjee, P.K. ; Davis, H.E. ; Hester, R.K. ; Malhi, S.D.S. ; Karnaugh, R. ; Gosmeyer, C.D. ; Sundaresan, R.S. ; Chen, C.E. ; Lam, H.W. ; Hake, R.A.

Author_Institution

Semiconductor Process and Design Center Texas Instruments Incorporated Dallas, Texas 75265

fYear

1984

fDate

10-12 Sept. 1984

Firstpage

Lastpage

Keywords

Boron; CMOS process; Etching; Geometry; Instruments; Lead compounds; Process design; Random access memory; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1984. Digest of Technical Papers. Symposium on

Conference_Location

San Diego, CA, USA

Print_ISBN

4-930813-08-5

Type

Filename

4480674

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