An ECL 4K-Bit Bipolar RAM with an Effective Access Time of 2.5NS and On-Chip Address Latches

Author

Yamaguchi, K. ; Kanetani, K. ; Todokoro, H. ; Nakano, T. ; Akimoto, K. ; Ogiue, K.

Author_Institution

Central Research Lab., Hitachi Ltd. Kokubunji, Tokyo, Japan

fYear

1984

fDate

10-12 Sept. 1984

Firstpage

Lastpage

Keywords

Circuit testing; Clocks; Delay effects; Driver circuits; Electron beams; Latches; Logic; Random access memory; Read-write memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1984. Digest of Technical Papers. Symposium on

Conference_Location

San Diego, CA, USA

Print_ISBN

4-930813-08-5

Type

Filename

4480695

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