Title :
An ECL 4K-Bit Bipolar RAM with an Effective Access Time of 2.5NS and On-Chip Address Latches
Author :
Yamaguchi, K. ; Kanetani, K. ; Todokoro, H. ; Nakano, T. ; Akimoto, K. ; Ogiue, K.
Author_Institution :
Central Research Lab., Hitachi Ltd. Kokubunji, Tokyo, Japan
Keywords :
Circuit testing; Clocks; Delay effects; Driver circuits; Electron beams; Latches; Logic; Random access memory; Read-write memory; Voltage;
Conference_Titel :
VLSI Technology, 1984. Digest of Technical Papers. Symposium on
Conference_Location :
San Diego, CA, USA
Print_ISBN :
4-930813-08-5
