Author_Institution :
Dept. of Electron. Eng., Nat. Taipei Univ. of Technol., Taipei, Taiwan
Abstract :
A concurrent 10.5/25 GHz power amplifier (PA) is designed and implemented in a 0.18 μm CMOS technology. This PA employs dual-band matching networks that can suppress harmonics, inter-modulation products, and out-of-band signals so as to improve linearity performances. Moreover, the driver stage of the PA utilises a current-reused topology which increases the gain without increase of the power dissipation. The chip size of the PA is 0.95 × 0.91 mm2 including testing pads, and its power consumption is 150 mW. The PA exhibits a measured gain of 15.2 and 6.8 dB, output P1dB of 10.5 and 9 dBm, Pout,max of 11.4 and 10 dBm and power added efficiency of 9 and 4.8% at 10.5 (f1) and 25 GHz (f2), respectively. The measured rejection of signals at 4 GHz (f2-2f1), 14.5 GHz (f2 - f1) and 21 GHz (2f1) is 43, 16.5 and 10.8 dB, respectively.
Keywords :
CMOS integrated circuits; harmonics suppression; intermodulation; microwave power amplifiers; CMOS technology; IMP; concurrent CMOS power amplifier; current-reused topology; driver stage; dual-band matching networks; efficiency 4.8 percent; efficiency 9 percent; frequency 10.5 GHz; frequency 14.5 GHz; frequency 21 GHz; frequency 25 GHz; frequency 4 GHz; gain 15.2 dB; gain 6.8 dB; harmonics suppression; intermodulation products; linearity performances; out-of-band signals; power 150 mW; size 0.18 mum;
