DocumentCode :
473013
Title :
System on Chip for Sensor Network Security: A Proposed Architecture
Author :
Sharma, Kalpana ; Varan, V. ; Kumar, Rohit
Author_Institution :
Sikkim Manipal Univ., Sikkim
Volume :
1
fYear :
2008
fDate :
17-20 Feb. 2008
Firstpage :
241
Lastpage :
245
Abstract :
The loss of confidential data results adversary effect while transmission in sensor network. The whole sensor network is then prone to get exposed to the intruder. Hence we need a strong mechanism, rather a hardware oriented solution to protect such sensitive data. In this paper we propose an alternative approach of securing data through an introduction of a hardware component called the linear feedback shift register (LFSR). The kind of network that we have considered is a hierarchical clustering sensor network. This technique mask all the intermediate, input and output data with some values in order to de-corelate information leaked, if any, so that the original/actual information is not exposed to the intruder. We propose an architecture embedded on a chip of the sensor node which is to be modified to incorporate a new component capable of generating random numbers to mask the output.
Keywords :
embedded systems; security of data; shift registers; system-on-chip; wireless sensor networks; embedded systems; hierarchical clustering sensor network; linear feedback shift register; sensor network security; system on chip; Data security; Hardware; Linear feedback shift registers; Propagation losses; Protection; Random number generation; Sensor systems; Shift registers; System-on-a-chip; Wireless sensor networks; LFSR; Sensor networks; data security; hierarchical clustering; randomization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Communication Technology, 2008. ICACT 2008. 10th International Conference on
Conference_Location :
Gangwon-Do
ISSN :
1738-9445
Print_ISBN :
978-89-5519-136-3
Type :
conf
DOI :
10.1109/ICACT.2008.4493753
Filename :
4493753
Link To Document :
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