FPGA Implementation of 3Mbps Single Carrier Mobile Wireless System with 1MHz Bandwidth

Author

NIshijo, Kunitoshi ; Syafei, Wahyul Amien ; Kurosaki, Masayuki ; Ochi, Hiroshi ; Ishii, Satoru

Author_Institution

Fac. of Comput. Sci. & Syst. Eng., Kyushu Inst. of Technol., Iizuka

Volume

2

fYear

2008

fDate

17-20 Feb. 2008

Firstpage

1060

Lastpage

1065

Abstract

In this paper, we present a FPGA implementation of single carrier (SC) wireless system with frequency domain equalization (FDE) to overcome the effects of multipath fading channels. We propose a new packet format for this wireless system to reduce the error of channel estimation that occurs in the last part of the packet caused by time fluctuation of the channel. Our targets are veracity 15 km/h and 3 Mbps data rate under 1 MHz bandwidth. Simulation results show that our proposed system can work in severe multipath fading with 33 Hz Doppler shift (15 km/h) and 6 ppm frequency offset environment. The logic synthesis result meets the specification.

Keywords

Doppler shift; channel estimation; fading channels; field programmable gate arrays; mobile communication; multipath channels; Doppler shift; FPGA implementation; bandwidth 1 MHz; bit rate 3 Mbit/s; channel estimation error; frequency domain equalization; multipath fading channels; single carrier mobile wireless system; Bandwidth; Channel estimation; Decision feedback equalizers; Fading; Field programmable gate arrays; Fluctuations; Frequency domain analysis; OFDM; Peak to average power ratio; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Communication Technology, 2008. ICACT 2008. 10th International Conference on

Conference_Location

Gangwon-Do

ISSN

1738-9445

Print_ISBN

978-89-5519-136-3

Type

conf

DOI

10.1109/ICACT.2008.4493949

Filename

4493949