A semi-empirical approach to determine the effective minimum current pulse width (T) for an operating silicon chip

In this paper we are going to discuss a semi-empirical approach, which will allow us, to determine the effective minimum time interval (T), over which voltage noise affects the performance of a silicon integrated circuit. This interval corresponds to simultaneous voltage collapse of the power delivery network, and current demand from the silicon. The current amplitude I₀ in this paper is assumed to be an average current drawn by the device when measured close to the power supply or close to the voltage regulator. This minimum time width (T) is equivalent to the amount of time the chip takes to ramp the current from 0 amps to some average current. This minimum current pulse width and current height can be used to construct various current waveforms generated by the device, including a step current.