Manufacturability Issues of Redundant Nanogates

Predicted device reliability for nanoelectronics indicates that redundant design will be necessary to build reliable nanosystems. The study of such systems requires the evaluation of the error probabilities associated to the fabrication process complexity. In this paper we compare two layouts for a basic NAND gate used to implement NAND Multiplexing (NM) redundant gates. To analyse the effects of the layouts, we derive models to calculate the error probability of each gate part according to the resolution errors of the manufacturing process. Our results indicate that gates built with diode-logic topologies are more reliable than gates built with CMOS like topologies and that the resolution errors limit the redundancy of practical NM gates.