Title :
An 8×8 run-time reconfigurable FPGA embedded in a SoC
Author :
Chaudhuri, Swarat ; Guilley, Sylvain ; Flament, F.
Author_Institution :
Philippe Hoogvorst & Jean-Luc Danger, GET-ENST, Paris
Abstract :
This paper presents a RTR FPGA embedded in a system on chip fabricated in 130 nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionality free of electrical conflicts, and we present a flow based on Altera synthesis tools to implement IPs(hardware blocks) in this FPGA. We demonstrate the full functionality with experiments on the FPGA, and as conclusion we highlight the limitations and future research directions.
Keywords :
CMOS integrated circuits; field programmable gate arrays; logic design; system-on-chip; Altera synthesis tools; CMOS process; SoC; field programmable gate arrays; run-time reconfigurable FPGA; size 130 nm; system-on-chip; CMOS process; Circuits; Design automation; Field programmable gate arrays; Fluid flow measurement; Hardware; Permission; Routing; Runtime; System-on-a-chip; FPGA; RTR;
Conference_Titel :
Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-60558-115-6
