• DocumentCode
    474437
  • Title

    DeFer: Deferred decision making enabled fixed-outline floorplanner

  • Author

    Yan, Jackey Z. ; Chu, Chris

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA
  • fYear
    2008
  • fDate
    8-13 June 2008
  • Firstpage
    161
  • Lastpage
    166
  • Abstract
    In this paper, we present DeFer - a fast, high-quality and non-stochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing floorplan. To find a good slicing floorplan, instead of searching through numerous slicing trees by simulated annealing as in traditional approaches, DeFer considers only one single slicing tree. However, we generalize the notion of slicing tree based on the principle of deferred decision making (DDM). When two subfloorplans are combined at each node of the generalized slicing tree, DeFer does not specify their orientations, the left-right/top-bottom order between them, and the slice line direction. DeFer even does not specify the slicing tree structures for small subfloorplans. In other words, we are deferring the decisions on these factors, which are specified arbitrarily at an early step in traditional approaches. Because of DDM, one slicing tree actually corresponds to a huge number of slicing floorplan solutions, all of which are efficiently kept in one single shape curve. With the final shape curve, it is straightforward to choose a good floorplan fitting into the fixed outline. Several techniques are also proposed to further optimize the wirelength. Experimental results on benchmarks with only hard blocks and with both hard and soft blocks show that DeFer achieves the best success rate, the best wirelength and the best runtime on average compared with other state-of-the-art floorplanners.
  • Keywords
    circuit layout; decision making; DeFer; deferred decision making enabled fixed-outline floorplanner; floorplan fitting; nonslicing floorplan; nonstochastic fixed-outline floorplanning algorithm; slicing trees; Algorithm design and analysis; Circuits; Computational modeling; Decision making; Distributed decision making; Permission; Runtime; Shape; Simulated annealing; Tree data structures; Deferred Decision Making; Fixed Outline; Floorplanning;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE
  • Conference_Location
    Anaheim, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-60558-115-6
  • Type

    conf

  • Filename
    4555801