SystemVerilog implicit port enhancements accelerate system design & verification

Author

Cummings, Clifford E.

Author_Institution

Sunburst Design, Inc., Beaverton, OR

fYear

2008

fDate

8-13 June 2008

Firstpage

231

Lastpage

236

Abstract

The IEEE Std 1800-2005 SystemVerilog standard added new implicit port instantiation enhancements that help accelerate top-level composition of large ASIC & FPGA designs. This paper details the new .* and .name implicit port instantiation capabilities, the rules related to the use of these new enhancements, and how these enhancements offer concise RTL coding styles while enforcing stronger port-type checking.

Keywords

application specific integrated circuits; field programmable gate arrays; hardware description languages; integrated circuit design; integrated circuit testing; logic CAD; logic testing; ASIC design; FPGA design; RTL coding styles; SystemVerilog standard; implicit port instantiation enhancement; port-type checking; system design; system verification; top-level composition; Acceleration; Application specific integrated circuits; Assembly; Design engineering; Field programmable gate arrays; Hardware design languages; Logic; Maintenance engineering; Sections; Web pages; .*; .name; SystemVerilog; Verilog; Verilog EMACS mode; implicit ports; instantiation;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE

Conference_Location

Anaheim, CA

ISSN

0738-100X

Print_ISBN

978-1-60558-115-6

Type

conf

Filename

4555814