Holistic pathfinding: Virtual wireless chip design for advanced technology and design exploration

As CMOS technology is scaled beyond 45 nm, SOC/SiP design for wireless chips is increasingly constrained by fundamental technology limits, resulting in challenges including parametric variability, leakage, active power, signal integrity, and diminished performance improvement. New materials and innovative device structures are needed to extend CMOS scaling and integrate disruptive "More than Moore" functionality, but these can have adverse impact on manufacturing cost and risk. Hence, tradeoff analysis spanning process, device, circuit, memory, package, architecture, software, and business disciplines is required during the advanced technology development cycle to explore and co-optimize technology and design choices. Such methodology, in conjunction with judicious use of test chips, also provides for a bridge from innovative technology solutions to mainstream product adoption. Several approaches are currently in use for ad-hoc exploration of advanced technology and design - typically based on spreadsheet analysis, guru consultation, and/or full trial designs. With the exploding complexity of the optimization space, subject matter knowledge and expert experience needs to be complemented with a structured methodology and tools. A "Holistic Pathfinding" methodology is proposed for addressing technology and design tradeoffs early in the development cycle to allow co-optimization all the way up to the system architecture level. A virtual design flow that allows rapid estimation of performance, power and cost attributes of a potential product, as a function of a given set of process or design assumptions is described as shown. Key target features of such a virtual flow and a summary of the attributes of several candidate point tools is presented. Requirements for the tools and methodologies to be used for Pathfinding across the span of disciplines are outlined, hi order to enable system cost and performance/power analyses, the requirements for predictive models that desc- - ribe variability, leakage, devices, interconnect, and DFM attributes are identified. Examples of Pathfinding application for co-optimization of memory technology and architecture, reduced parametric variability using restricted physical design rules, and exploration of 3D chip stacking are presented to highlight the requirements and gaps in the existing EDA tool solutions. The vision is for a design exploration platform that outputs performance, active and standby power, and cost estimates in reasonable response time, and with physical and variation awareness at the architectural level.