DocumentCode
474566
Title
Phase-adjustable Error Detection Flip-Flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling
Author
Kurimoto, Masanori ; Suzuki, Hiroaki ; Akiyama, Rei ; Yamanaka, Tadao ; Ohkuma, Haruyuki ; Takata, Hidehiro ; Shinohara, Hirofumi
Author_Institution
Renesas Technol. Corp., Hyogo
fYear
2008
fDate
8-13 June 2008
Firstpage
884
Lastpage
889
Abstract
Error detection FFs for dynamic voltage scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.
Keywords
buffer circuits; delay circuits; driver circuits; error detection; flip-flops; 2-stage hold driven optimization; clock phase; delay buffers; dynamic voltage scaling; energy consumption; error signal latency; phase-adjustable error detection flip-flops; power penalties; slack based grouping scheme; Circuits; Clocks; Delay; Dynamic voltage scaling; Error correction; Flip-flops; Phase detection; Signal design; Timing; Voltage control; CTS; DVS; Error-Detection Flip-Flop; STA;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
978-1-60558-115-6
Type
conf
Filename
4555944
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