Fast deblocking filter implementation method and it’s architecture for H.264/AVC

In this work, a fast implementation method for deblocking filter of H.264/AVC and its architecture are proposed. Proposed method makes use of the correlation of the adjacent pixels to decrease the redundant processing cycles. Simulation results show that using proposed method, the average coding cycles for one macroblock is reduced to 170. It is fast than that of the previous works which considered that the least filtering cycles number for one macroblock is 192. This work also provide an efficient architecture for the proposed method in which a parallel memory access solution and a novel comparison module are proposed. Implementation results show that the proposed architecture can be realized by only 30.14 K gates.