A multiplying-by-two CMOS amplfifier for high-speed ADCs based on parametric amplification

In this paper a new structure for a multiplying-by-two amplifier is proposed. It is implemented by switching MOS capacitors with floating sources from inversion into depletion dropping the capacitance values in the amplification phase. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used to provide the required isolation. Simulation results show that linearity levels better than 60dB and gain accuracies of better than 1.6% are achieved making this circuit well suited to be used in ultra low-power high-speed 6-to-8 bits pipeline or multi-stage algorithmic ADCs.