An asynchronous SystemC library and control data flow extraction

The lack of commercial CAD tools and design methodology has hindered the wide use of asynchronous designs. A high level language capable of synthesizing asynchronous circuits in a transparent manner could attract engineers to benefit from asynchronous design advantages. In this paper, a SystemC library is developed as an extension to the existing SystemC language to enable asynchronous circuit description at the highest level of abstraction. For this purpose, building blocks of asynchronous circuits are introduced into the library. This library resides on the top of the transition layer that bridges the gap between the high level language compilation and hardware synthesis. A tool which extracts from the high level description optimized control flow graph and data flow graphs has been developed. The proposed library enables the modelling and designing of efficient asynchronous circuits at a high level without having to deal with detail of asynchronous implementations. Extracted CFG and DFG was prepared in well-defined form that can easily be used for synthesis purpose, verification or test generation in later steps of our digital design flow.