DocumentCode
476158
Title
A new dynamic reconfigurable technology to reduce power dissipation
Author
Wang, Yil-ei ; Li, Tao ; Liu, Chan-juan ; Li, Hong-guo
Author_Institution
Dept. of Comput. Sci. & Technol., Lu Dong Univ., Yantai
Volume
4
fYear
2008
fDate
12-15 July 2008
Firstpage
2202
Lastpage
2205
Abstract
This paper first describes the reconfigurable technology related research field and the research significance on SoC Cache. Then gives the collectivity structure of SoC2000, processor reconstruct, double nuclear communication model and interlinkage style, induct scheme, synchronization method and principle and subordinate CPU nuclear clock mutual close. This new technology can improve batches rate of CMOS chips.
Keywords
CMOS integrated circuits; low-power electronics; synchronisation; system-on-chip; CMOS chips; SoC cache; double nuclear communication model; dynamic reconfigurable technology; power dissipation reduction; processor reconstruction; synchronization; Application software; CMOS technology; Costs; Cybernetics; Encapsulation; Hardware; Machine learning; Power dissipation; Programming profession; Random access memory; CMOS Chip; Power Dissipation; Reconfigurable Technology; Soc;
fLanguage
English
Publisher
ieee
Conference_Titel
Machine Learning and Cybernetics, 2008 International Conference on
Conference_Location
Kunming
Print_ISBN
978-1-4244-2095-7
Electronic_ISBN
978-1-4244-2096-4
Type
conf
DOI
10.1109/ICMLC.2008.4620771
Filename
4620771
Link To Document