Design optimization of DWT structure for implementation of image compression techniques

The optimal VLSI architecture and algorithm for computing lifting based wavelet is presented. For the (5, 3) filter, the division by four or by two is implemented with look-up table (LUT). But for the (9, 7) filter, the operation is more complex. We present the fragment look-up table algorithm implements the multipliers. The algorithm can reuse the small memory to realize high precision for the multipliers (scaling by K or 1/K). Experimental results demonstrated that the proposed approach is effective in reduce chip size and power consume. The algorithm is also simpler and faster, and can be implemented easily for SOC integration.