DocumentCode
477170
Title
Theoretical analysis of power clock generator based on the switched capacitor regulator for adiabatic CMOS logic
Author
Takahashi, Yasuhiro ; Sekine, Toshikazu ; Yokoyama, Michio
Author_Institution
Dept. of Electr. & Electron. Eng., Gifu Univ., Gifu
fYear
2008
fDate
18-19 Sept. 2008
Firstpage
17
Lastpage
22
Abstract
This paper reports an analytical method of a power clock generator based on a switched capacitor circuit which is used in adiabatic logic. We derive first an equivalent circuit model of the switched capacitor circuit. We then discuss the design optimization of the capacitance ratio. Finally, we show that the analytical results agree rather well with the SPICE simulation results.
Keywords
CMOS logic circuits; clocks; equivalent circuits; switched capacitor networks; SPICE simulation; adiabatic CMOS logic; capacitance ratio; design optimization; equivalent circuit model; power clock generator; switched capacitor circuit; switched capacitor regulator; CMOS logic circuits; Capacitance; Clocks; Design optimization; Equivalent circuits; Logic circuits; Power generation; Regulators; Semiconductor device modeling; Switched capacitor circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Micro-Nanoelectronics, Technology and Applications, 2008. EAMTA 2008. Argentine School of
Conference_Location
Buenos Aires
Print_ISBN
978-987-655-003-1
Electronic_ISBN
978-987-655-003-1
Type
conf
Filename
4638970
Link To Document