Improved hardware implementation of a complementary sequences generator and correlator

Complementary sequences are currently being applied to multiple fields of engineering. Given their particular mathematical properties, they have been widely used in applications ranging from robotics to communications, and have even been implemented in programmable logic devices (e.g. FPGA). Most of the applications proposed in the literature need to employ efficient architectures to reduce the computational load. This paper describes improved generator and correlator architectures which result in hardware requirements reduction when implemented in FPGAs.