VLSI microprocessor architecture for a simplicial PWL function evaluation core

Author

Rodriguez, J.A. ; Julian, P. ; Lifschitz, O. ; Agamennoni, O. ; Jimenez-Fernandez, V.M.

Author_Institution

Dept. de Ing. Electr. y de Computadoras, Univ. Nac. del Sur, Bahia Blanca

fYear

2008

fDate

18-19 Sept. 2008

Firstpage

55

Lastpage

60

Abstract

In this paper, we present a VLSI design for a piecewise linear (PWL) function evaluator. This design is based on a dedicated microprocessor architecture that allows re- programmability not only in the function, but also in the dimension (n = 1, . . . . , 6). The design was developed by using industry electronic design automation (EDA) tools and a standard CMOS 0.5 mum technology. Logic and analog simulations show the correct operation of the design.

Keywords

CMOS integrated circuits; VLSI; electronic design automation; microcomputers; piecewise linear techniques; CMOS technology; PWL function evaluation core; VLSI microprocessor; analog simulations; electronic design automation tools; logic simulations; piecewise linear functions; programmability; size 0.5 mum; CMOS technology; Computer architecture; Electronic design automation and methodology; Electronics industry; Microprocessors; Optical computing; Optical design; Piecewise linear techniques; Standards development; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Micro-Nanoelectronics, Technology and Applications, 2008. EAMTA 2008. Argentine School of

Conference_Location

Buenos Aires

Print_ISBN

978-987-655-003-1

Electronic_ISBN

978-987-655-003-1

Type

conf

Filename

4638977