28.8 dBm, High Efficiency, Linear GaN Power Amplifier With In-Phase Power Combining for IEEE 802.11p Applications

This letter presents a power amplifier (PA) for IEEE802.11p applications, adopting a new power combining technique in a 250 nm GaN process. The proposed technique is used to improve the drain efficiency (DE) across the output power levels and meet the stringent error vector magnitude (EVM) requirement without any complicated input and output networks. The PA is implemented with a fabricated GaN die using the chip-on-board (COB) technology and tested with 27 Mbps IEEE802.11p signal. It achieves -30.5 dB EVM at 28.8 dBm output power with a back-off DE of 22.4% at 30 V supply at 5.72 GHz without pre-distortion. It also maintains more than 22% DE through supply voltage control while meeting its linearity requirement across the wide range of output power levels. The proposed circuit technique is viable for improving efficiency and optimizing linearity with its simple architecture.