Design and Implementation of Memory Pools for Embedded DSP

Two sorts of pool memory are developed for the needs of programming reconfigurable embedded DSP applications. One-piece signal free list and first-fit police are used in the designed of equal size memory pool in which the search time of a free block is faster than c-runtime allocator. Based on two-level segregated fit algorithm, unequal size memory pool is implemented for the requirements of low fragmentation and bounded responded times. The boundary of memory block allocated can be four words aligned. For making the allocation polices adaptable to various DSP hardware resource and DSP applications, a reusable software framework used for management of memory pools is presented. Pattern and bridge design pattern are used in the designing of frame strategy work. The memory allocation algorithm can be selected according to DSP application and DSP memory resources. As a result, DSP embedded system developers can create multiple allocators for a signal complex application. The software framework and the algorithm are applied for ADTS101 DSP hardware platform.