Title :
A Verifying Method of Controller Synthesis
Author :
Li Wei ; Lu Ying ; Zhang Yi-chao ; Wu Jian-guo
Author_Institution :
Inst. of Comput. Sci. & Technol., Anhui Univ., Hefei
Abstract :
Verifying of controller synthesispsila correctness is studied in this paper, which is based on completely specified finite state machine. We obtain some useful information by verifying two graphsdasia isomorphism, which is about the corresponding controller synthesispsila correctness. First get behavior description by inverse analyzing, then design a verifying method based on STGpsilas (state transition graph) isomorphism, finally analyzing the time complexity.
Keywords :
computational complexity; finite state machines; formal verification; graph theory; controller synthesis correctness; finite state machine; formal verification; graph isomorphism; state transition graph; time complexity; Analytical models; Automata; Automatic control; Circuit simulation; Circuit testing; Computer science; Control system synthesis; Digital systems; Information analysis; System testing; Controller Synthesis; Finite State Machine; State Transition Graph; Verification;
Conference_Titel :
Computer Science and Software Engineering, 2008 International Conference on
Conference_Location :
Wuhan, Hubei
Print_ISBN :
978-0-7695-3336-0
DOI :
10.1109/CSSE.2008.812
