Advanced Optimization and Design Issues of a 32-Bit Embedded Processor Based on Produced Order Queue Computation Model

Queue computing based programs are generated using a so called level order traversal that exposes all available parallelism in the programs. All instructions within the same level are data independent from each other and are safely to be executed in parallel. This property is leveraged by the compiler generating queue programs with high amounts of grouped independent instructions. Thus, the hardware invests little efforts to find parallelism. In this paper, we present various optimization and design issues of a synthesizable queue processor architecture targeted for embedded applications. A prototype implementation is produced by synthesizing the high-level model for a target FPGA device.