Title :
Voltage clamping requirements for ESD protection of inputs in 90nm CMOS technology
Author :
Lee, Jeffrey ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL
Abstract :
ESD reliability of MOS gate dielectrics and of input circuitry is investigated for a 90 nm CMOS technology. Performance degradation is observed at voltages lower than the breakdown voltage. It is found that the input transistor gate dielectric breakdown voltage depends strongly on the source-body voltage and, consequently, on the input circuit design.
Keywords :
CMOS integrated circuits; dielectric thin films; electric breakdown; electrostatic discharge; integrated circuit reliability; integrated circuit testing; CMOS technology; MOS gate dielectrics; dielectric breakdown; electrostatic discharge protection; performance degradation; voltage clamping; Breakdown voltage; CMOS technology; Circuits; Clamps; Dielectrics; Electrostatic discharge; MOS devices; MOSFETs; Protection; Stress;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-58537-146-4
Electronic_ISBN :
978-1-58537-147-1
