Title :
Wafer-level Charged Device Model testing
Author :
Chou, Bruce C. ; Maloney, Timothy J. ; Chen, Tze Wee
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
Charged Device Model (CDM) ESD testing is demonstrated on wafer level. With a custom probe-mounted printed-circuit board and a high-frequency transformer that captures fast CDM pulses, wafer-level CDM (WCDM) pulses are applied and monitored repeatably. Modeling of CDM and WCDM in the time and frequency domain illustrates the dominant effects, and shows that WCDM can reproduce all the major phenomena of package-level CDM testing.
Keywords :
electrostatic discharge; high-frequency transformers; integrated circuit modelling; integrated circuit testing; printed circuits; ESD testing; frequency domain; high-frequency transformer; probe-mounted printed-circuit board; time domain; wafer-level charged device model testing; Capacitance; Circuit testing; Electrostatic discharge; Instruments; Integrated circuit modeling; Probes; Pulse transformers; Semiconductor device modeling; Switches; Thyristors;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-58537-146-4
Electronic_ISBN :
978-1-58537-147-1
