DocumentCode
483357
Title
The challenges of on-chip protection for system level cable discharge events (CDE)
Author
Lin, Yen-Yi ; Park, Jae ; Isachar, Ori ; Chaikin, Shlomy ; Chundru, Ram ; Duvvury, Charvaka ; Marum, Steve ; Diep, Tom
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
2008
fDate
7-11 Sept. 2008
Firstpage
125
Lastpage
131
Abstract
The CDE stress for on-chip protection is evaluated with the design of a TI internal CDE tester. Comparison with a long-pulse TLP indicated non-correlation for the failure current but better tracking with the failure voltage. However, both the on-board magnetics and board design can also influence the failure threshold level.
Keywords
electrostatic discharge; failure analysis; integrated circuit design; integrated circuit testing; CDE stress; TI internal CDE tester; board design; failure current; failure threshold level; failure voltage; long-pulse TLP; on-board magnetics; on-chip protection; system level cable discharge events; Communication cables; Ethernet networks; Power cables; Protection; Relays; Stress; System testing; System-on-a-chip; Transceivers; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th
Conference_Location
Tucson, AZ
Print_ISBN
978-1-58537-146-4
Electronic_ISBN
978-1-58537-147-1
Type
conf
Filename
4772124
Link To Document