Title :
Capacitance investigation of diode and GGNMOS for ESD protection of high frequency circuits in 45nm SOI CMOS technologies
Author :
Li, Junjun ; Mitra, Souvick ; Li, Hongmei ; Abou-Khalil, Michel J. ; Chatty, Kiran ; Gauthier, Robert
Author_Institution :
IBM Semicond. R&D Center, Essex Junction, VT
Abstract :
S-parameter test structures from a 45 nm SOI CMOS technology show total capacitance per perimeter of poly-bounded ESD diodes ranges from ~0.35-0.42 fF/mum, and silicide-block (SBLK) bounded diodes show ~15-20% capacitance reduction. Floating-body or notched-silicon tied-body Gate-Silicided GGNMOS devices show total capacitance per width of ~0.65 fF/um for thin oxide devices, and ~0.72 fF/mum for thick oxide devices. Gate-Non-Silicided devices have ~20% higher capacitance because of increased junction area.
Keywords :
CMOS integrated circuits; S-parameters; electrostatic discharge; semiconductor diodes; silicon-on-insulator; ESD protection; S-parameter test structures; SOI CMOS technologies; floating-body; gate-silicided GGNMOS devices; high frequency circuits; notched-silicon tied-body; poly-bounded ESD diodes; silicide-block bounded diodes; size 45 nm; thin oxide devices; CMOS technology; Capacitance; Circuit testing; Electrostatic discharge; Performance evaluation; Protection; Radio frequency; Scattering parameters; Semiconductor diodes; Silicon;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-58537-146-4
Electronic_ISBN :
978-1-58537-147-1
