Title :
ESD device design strategy for high speed I/O in 45nm SOI technology
Author :
Cao, Shuqing ; Salman, Akram A. ; Beebe, Stephen G. ; Pelella, Mario M. ; Chun, Jung-Hoon ; Dutton, Robert W.
Author_Institution :
Integrated Circuits Lab., Stanford Univ., Stanford, CA
Abstract :
This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45 nm silicon on insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.
Keywords :
electrostatic discharge; field effect devices; high-speed techniques; nanoelectronics; semiconductor device breakdown; semiconductor device testing; semiconductor diodes; silicon-on-insulator; technology CAD (electronics); ESD device design strategy; ESD protection devices; SOI technology; Si-JkJk; bulk substrate diode; double-well field-effect diode; gated diode; high-speed I/O application; silicon-on-insulator technology; size 45 nm; technology computer aided design; very-fast transmission line pulse test; Breakdown voltage; CMOS technology; Capacitance; Design methodology; Diodes; Electrostatic discharge; Integrated circuit modeling; Protection; Silicon on insulator technology; Testing;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-58537-146-4
Electronic_ISBN :
978-1-58537-147-1
