Design methodology of FinFET devices that meet IC-Level HBM ESD targets

Author

Thijs, S. ; Russ, C. ; Trémouilles, D. ; Griffoni, A. ; Linten, D. ; Scholz, M. ; Collaert, N. ; Rooyackers, R. ; Jurczak, M. ; Sawada, M. ; Nakaei, T. ; Hasebe, T. ; Duvvury, C. ; Gossner, H. ; Groeseneken, G.

Author_Institution

Electr. Eng. Dept., Katholieke Univ. Leuven, Leuven

fYear

2008

fDate

7-11 Sept. 2008

Firstpage

294

Lastpage

302

Abstract

A new design methodology for FinFET devices is presented which takes into account all complex dependencies on both layout and process parameters of the electrical ESD device parameters of FinFET gated diodes and NMOS FinFET devices in both parasitic bipolar and active MOS operation mode. This methodology allows optimization towards a given ESD target (area consumption, leakage current, parasitic capacitance,...) while fulfilling several imposed design constraints. KiloVolt HBM levels in FinFETs are demonstrated meeting the full IC-level ESD requirements.

Keywords

MOS integrated circuits; MOSFET; bipolar transistors; electrostatic discharge; leakage currents; semiconductor diodes; FinFET gated diodes; IC-level HBM ESD targets; NMOS FinFET devices; active MOS operation mode; area consumption; leakage current; parasitic bipolar; parasitic capacitance; Constraint optimization; Design engineering; Design methodology; Design optimization; Electrostatic discharge; FinFETs; Leakage current; MOSFETs; Parasitic capacitance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th

Conference_Location

Tucson, AZ

Print_ISBN

978-1-58537-146-4

Electronic_ISBN

978-1-58537-147-1

Type

conf

Filename

4772147