DocumentCode
483382
Title
ESD protection using grounded gate, gate non-silicided (GG-GNS) ESD NFETs in 45nm SOI technology
Author
Mitra, Souvick ; Gauthier, Robert ; Li, Junjun ; Abou-Khalil, Michel ; Putnam, Chris S. ; Halbach, Ralph ; Seguin, Christopher
Author_Institution
IBM Microelectron. Semicond. R&D Center, Essex Junction, VT
fYear
2008
fDate
7-11 Sept. 2008
Firstpage
312
Lastpage
316
Abstract
A non-self protection ESD scheme using grounded-gate, gate non-silicided (GG-GNS) drain/source silicide blocked (SBLK) ESD NFET offered in 45 nm SOI CMOS technology is presented based on a comprehensive study using the high current pulse characteristics. The results show that with a minimum SBLK width over drain/source, GG-GNS NFET can handle ~3.4 mA/mum current.
Keywords
CMOS integrated circuits; electrostatic discharge; integrated circuit testing; silicon-on-insulator; CMOS technology; drain/source silicide blocked NFET; electrostaitc discharge protection; electrostatic discharge protection; grounded-gate; silicon-on-insulator; CMOS technology; Electrostatic discharge; Fingers; Implants; Integrated circuit technology; Protection; Semiconductor diodes; Silicides; Variable structure systems; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2008. EOS/ESD 2008. 30th
Conference_Location
Tucson, AZ
Print_ISBN
978-1-58537-146-4
Electronic_ISBN
978-1-58537-147-1
Type
conf
Filename
4772149
Link To Document