A.1 ESD protection targets

In light of the work from the Industry Council on ESD Target Levels it has become clear that the ESD protection designs for the IC pins may be carrying an unnecessary burden. This burden becomes a problem when the IC circuits are trying to meet speed and performance demands. Through this workshop we will review the current ESD requirements for HBM, MM and CDM and discuss the reasons why this load must be shifted to better ESD control methods while defining the realistic specification targets for each stress model. The audience participation will be involved to address the following questions. What are the realistic component IC ESD requirements? How should the ESD designers and IC designers work together to achieve these? At what levels do the designs become impossible? What types of circuits are intolerable to even minimum ESD targets? Are the ESD designers responsible for system level protection also?