C.3 The challenge of CDM testing

CDM is recognized as the main ESD threat in today’s electronics manufacturing environment. Unfortunately CDM is increasingly seen as immature. There are competing standards: JEDEC and ESDA versions of Field Induced CDM (F-CDM), JEITA’s direct charging CDM and even use of the Socketed Device Model, each producing different failure thresholds. F-CDM, the most widely accepted, has numerous technical challenges. Air discharge in F-CDM has inherent variability, F-CDM is a challenge for small and odd shaped devices, the pulse size does not scale with C for large packages and waveforms that look excellent at 1GHz have higher frequency components that can affect test results. Meanwhile designers face limits on the current that can be carried during a CDM event. This workshop will allow panelists and attendees to express concerns and describe a path to a better CDM test environment.