Title :
A monolithic 10-Gb/s CMOS limiting amplifier for low cost optical communication systems
Author :
Liang, Bangli ; Kwasniewski, Tad ; Wang, Zhigong ; Chen, Dianyong ; Wang, Bo ; Cheng, Dezhong
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, ON
Abstract :
In this paper, a 10-Gb/s limiting amplifier (LA) was implemented in 0.18 mum CMOS. Modified active inductors and active feedback topology are employed to eliminate the trade-off among circuit bandwidth, power dissipation, and layout area, which is suitable for low cost applications. Based on the measurement results, the realized LA can operate up to 12-Gb/s with a 125 mVpp single-ended output through equivalent 25-Omega load. The input dynamic range is 40 dB corresponding to the signal level range from 4 mV to 400 mV. The RMS jitter of the output signal is 2 ps and the total power dissipation (including output buffer) is only 60 mW under a supply of 1.8 V.
Keywords :
CMOS integrated circuits; amplifiers; network topology; optical receivers; RMS jitter; active feedback topology; active inductors; bit rate 10 Gbit/s; monolithic CMOS limiting amplifier; optical communication system; optical receiver; power 60 mW; power dissipation; size 0.18 mum; voltage 1.8 V; Active inductors; Bandwidth; Circuit topology; Costs; Feedback circuits; Optical amplifiers; Optical feedback; Optical fiber communication; Power dissipation; Semiconductor optical amplifiers;
Conference_Titel :
Communications, 2008. APCC 2008. 14th Asia-Pacific Conference on
Conference_Location :
Tokyo
Print_ISBN :
978-4-88552-232-1
Electronic_ISBN :
978-4-88552-231-4
