Design and implementation of pipelined DRR ASIC

Author

Hsiao, Yi-Mao ; Chen, Ming-Jen ; Chen, Yier ; Chu, Yuan-Sun ; Wu, Cheng-Shong

Author_Institution

Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chiayi

fYear

2008

fDate

14-16 Oct. 2008

Firstpage

1

Lastpage

4

Abstract

In this paper, a novel scheme called pipelined deficit round robin (PDRR) is proposed for packet scheduler. We reorder the processing stages and use the pipelined method to reduce the delay time. The scheme preserves O(1) complexity in hardware. By the simulation result, PDRR has 60% improvement better delay time than DRR. The ASIC operates approximately 3.5 ns by 0.18 um CMOS technology and supplied with 1.8 V and power dissipation is 47 mW. The area is 0.845 mm times 0.879 mm involving pads. It can furnish approximately 285.71 MHz so that is enough to satisfy OC-768.

Keywords

CMOS integrated circuits; application specific integrated circuits; delays; CMOS technology; delay time; packet scheduler; pipelined DRR ASIC; pipelined deficit round robin; power 47 mW; size 0.18 mum; voltage 1.8 V; Application specific integrated circuits; CMOS technology; Delay effects; Hardware; Laboratories; Power dissipation; Quality of service; Round robin; Scheduling algorithm; Web and internet services; ASIC; Quality of Service; pipelined DRR; scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 2008. APCC 2008. 14th Asia-Pacific Conference on

Conference_Location

Tokyo

Print_ISBN

978-4-88552-232-1

Electronic_ISBN

978-4-88552-231-4

Type

conf

Filename

4773751