• DocumentCode
    483596
  • Title

    Optimize transistor size for FIR pre-emphasis with programmable coefficients

  • Author

    Cheng, Dezhong ; Liang, Bangli ; Chen, Dianyong ; Kwasniewski, Tad

  • Author_Institution
    Dept. of Electron., Carleton Univ., Ottawa, ON
  • fYear
    2008
  • fDate
    14-16 Oct. 2008
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    A finite impulse response (FIR) 6-tap pre-emphasis (PEP) filter with programmable coefficients was employed to counteract intersymbol interface (ISI) in high speed backplane data communication or optical communication. The proposed circuit can operate at the data rates up to 10 Gb/s. This circuit is designed in 90 nm CMOS technology and operates at 1.0 V. Simulation results show that the circuit improves signal eye diagram opening by at least 120 mV at receiver end for the B mode channel from IEEE P802.3 ap Task Force Channel Model Material. The total power consumption is 41.2 mW for the whole pre-emphasis, including the retiming circuit and the pre-drive buffers.
  • Keywords
    CMOS digital integrated circuits; FIR filters; programmable filters; transistors; CMOS technology; FIR pre-emphasis; IEEE P802.3ap Task Force Channel Model Material; bit rate 10 Gbit/s; finite impulse response filter; high speed backplane data communication; intersymbol interface; optical communication; power 41.2 mW; pre-drive buffers; programmable coefficients; retiming circuit; size 90 nm; transistor size optimization; voltage 120 mV; Backplanes; CMOS technology; Circuit simulation; Data communication; Finite impulse response filter; Intersymbol interference; Optical fiber communication; Optical filters; Signal analysis; Signal design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, 2008. APCC 2008. 14th Asia-Pacific Conference on
  • Conference_Location
    Tokyo
  • Print_ISBN
    978-4-88552-232-1
  • Electronic_ISBN
    978-4-88552-231-4
  • Type

    conf

  • Filename
    4773761