Title :
A New Super Junction LDMOS with N+-Floating Layer
Author :
Duan, Baoxing ; Zhang, Bo ; Li, Zhaoji
Author_Institution :
Res. Inst. of Micro-Electron., Univ. of Electron. Sci. & Technol. of China, Chengdu
Abstract :
A new CMOS compatible super junction LDMSOT structure is designed with N+-floating layer embedded in the high-resistance substrate, which suppresses charges imbalance effect resulting from substrate-assisted depletion N-type pillar, and the high electric field around the drain is reduced by N+-floating layer which causes the redistribution of the bulk electric field in the drift region. The new structure features high breakdown voltage, low on resistance and charges balance in drift region due to N+-floating layer
Keywords :
CMOS integrated circuits; electric breakdown; power MOSFET; semiconductor junctions; N+-floating layer; breakdown voltage; charge imbalance effect; electric field redistribution; substrate-assisted depletion; super junction LDMOS; Breakdown voltage; CMOS technology; Degradation; Doping; Electric breakdown; Electric resistance; MOSFETs; Silicon; Substrates; N+-Floating Layer; Super Junction; substrate-assisted depletion;
Conference_Titel :
Power Electronics and Motion Control Conference, 2006. IPEMC 2006. CES/IEEE 5th International
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0448-7
DOI :
10.1109/IPEMC.2006.4777949
