DocumentCode :
48385
Title :
Secure distribution infrastructure for hardware digital contents
Author :
Cilardo, Alessandro ; Barbareschi, Mario ; Mazzeo, Antonino
Author_Institution :
DIETI, Univ. Federico II, Naples, Italy
Volume :
8
Issue :
6
fYear :
2014
fDate :
11 2014
Firstpage :
300
Lastpage :
310
Abstract :
Field-programmable gate array (FPGA) reconfigurability creates the possibility of distributing hardware cores pretty much like software digital contents, possibly on payment or on a subscription basis. In this work, the authors propose an infrastructure for the secure distribution of such hardware digital contents (HDCs). Aimed at the practical realisation of the envisioned scenario, this study analyses the security-related features of the current FPGA devices, for example, (partial) bitstream encryption, and takes them as the underlying constraints for the definition of the infrastructure. This work clearly identifies the roles involved in the secure distribution process, including a trusted third-party entity, and introduces a cryptographic protocol ensuring the confidentiality and the trustworthiness of partial bitstreams dynamically downloaded to the user´s device. This study also presents a detailed case-study application scenario, namely the secure distribution of image codec components, providing a few quantitative results and demonstrating the limited overhead incurred by the proposed solution in terms of time and area costs. The conclusive section of this study discusses the lesson learned from this work and draws a few proposals for the evolution of security-related FPGA features which may enable the full realisation of the secure HDC distribution concept.
Keywords :
codecs; cryptographic protocols; field programmable gate arrays; image coding; FPGA devices; HDCs; area costs; bitstream encryption; cryptographic protocol; field-programmable gate array reconfigurability; hardware core distribution; hardware digital contents; image codec components; partial bitstreams; secure distribution infrastructure process; security-related FPGA features; security-related features; trusted third-party entity; user device;
fLanguage :
English
Journal_Title :
Computers & Digital Techniques, IET
Publisher :
iet
ISSN :
1751-8601
Type :
jour
DOI :
10.1049/iet-cdt.2014.0036
Filename :
6962955
Link To Document :
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