DocumentCode :
484753
Title :
Adaptivity and reliability in future chips. Multi-core and reconfigurable architectures in the Nano Era
Author :
Becker, J.
Author_Institution :
Karlsruhe Inst. of Technol., Karlsruhe
fYear :
2008
fDate :
18-19 June 2008
Firstpage :
2
Lastpage :
2
Abstract :
Summary form only given. The field of embedded electronic systems is still emerging. Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore\´s benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy and cost constraints. The author\´s view is of an "all-win-symbiosis" of future silicon- based processor technologies and reconfigurable circuits/architectures. Dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing high adaptivity for a range of applications and situations. Reliability, failure-redundancy and run-time adaptivity using real-time hardware reconfiguration are important aspects for current and future systems. Thus, scalability, as we have experienced for the last 35 years is at its end as we enter the so-called Nano Era. Beyond the capabilities of traditional reconfigurable fabrics (like FPGAs), nano circuits/architectures allow for micro-mechanical switches that enable new memory and reconfiguration technologies with the advantage of online chip adaptivity and non-volatility. The deployment of new 3-D nano structures and materials promises higher integration densities and is considered advantageous for signal delays. Yield is significantly lower, and could, as we define it in the classical sense, eventually be nil! Transient faults may lead to unreliable information processing as information in nano-sized devices is much less. Power consumption and related problems present a challenge where information is processed within a smaller area/volume budget. Thus, novel design methodologies, novel adaptive mechanisms which solve operation-time shortcomings, and novel computing paradigms are necessary. Fault tolerance/correction in all its facets is key and should be considered an inherent techniqu- i
Keywords :
embedded systems; fault tolerance; integrated circuit design; integrated circuit reliability; low-power electronics; nanoelectronics; reconfigurable architectures; system-on-chip; 3D nanomaterials; 3D nanostructures; adaptive systems-on-chip; all-win-symbiosis; chip reliability; design methodologies; dynamic reconfiguration; embedded electronic systems; failure-redundancy; fault correction; fault tolerance; general purpose systems; multicore architectures; multipurpose chip adaptivity; nanocircuits; partial reconfiguration; power consumption; reconfigurable architectures; reconfigurable circuits; reconfigurable computing technologies; reliable systems-on-chip; silicon-based processor technologies; transient faults;
fLanguage :
English
Publisher :
iet
Conference_Titel :
Signals and Systems Conference, 208. (ISSC 2008). IET Irish
Conference_Location :
Galway
ISSN :
0537-9989
Print_ISBN :
978-0-86341-931-7
Type :
conf
Filename :
4780920
Link To Document :
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