Architecture of efficient RNS-based digital signal processor with very low-level pipelining

A generalized architecture of an efficient digital signal processor using the residue number system (RNS) is proposed. It is based on using our new residue multipliers-accumulators (MACs) as the main building blocks. This architecture offers potentially higher throughput thanks to the possibility of implementing very low-level pipelining. The maximal applicable clock frequency could be determined by the delay of only a few stages of full-adders.