Algorithm for adjustment of DDR write interface timing

While the demand for memory capacity and performance continues to increase, current DDR-2 memory implementations start to encounter limitations. At high data rates of 533 MT/s and above, it becomes increasingly difficult to support greater than two DIMMs on a single DDR channel due to board routing and timing constraints. Supporting different combinations of DDR-2 raw card types on the same platform also complicates the timing and routing due to the possible variations in load. This paper outlines a method of achieving higher data rates of DDR-2 while supporting multiple DIMM configurations on a single platform by utilizing hardware circuitry in the memory controller in connection with software algorithms to adjust the DDR signal timing relationships based on the populated memory configuration. The algorithm also compensate for the effects of ageing over the lifetime of the part. The techniques used in this work are related to DDR-2 but could also be applicable to DDR-3 and future technologies.