DocumentCode
484783
Title
An optimal IEEE 1500 core wrapper design for improved test access and reduced test time
Author
Mullane, B. ; Higgins, M. ; MacNamee, C.
Author_Institution
Dept. of Electron. Comput. Eng., Univ. of Limerick, Limerick
fYear
2008
fDate
18-19 June 2008
Firstpage
204
Lastpage
209
Abstract
IEEE 1500 test wrappers that enable higher test bandwidth capability, system bus connectivity and efficient test vector organization are presented. Embedded core wrappers and test vectors that seamlessly work with ASIC and FPGA design flows are illustrated. Implementation and test-chip design show the positive impact on test time with potential for minimal wiring and logic overhead savings.
Keywords
application specific integrated circuits; field programmable gate arrays; system-on-chip; wrapping; ASIC; FPGA design flows; embedded core wrappers; high test bandwidth capability; logic overhead savings; optimal IEEE 1500 core wrapper design; reduced test time; system bus connectivity; test vector organization; test-chip design; ASIC; Core Test; DFT; FPGA Prototyping; IEEE 1500; SoC Test;
fLanguage
English
Publisher
iet
Conference_Titel
Signals and Systems Conference, 208. (ISSC 2008). IET Irish
Conference_Location
Galway
ISSN
0537-9989
Print_ISBN
978-0-86341-931-7
Type
conf
Filename
4780954
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