Title :
An optimal IEEE 1500 core wrapper design for improved test access and reduced test time
Author :
Mullane, B. ; Higgins, M. ; MacNamee, C.
Author_Institution :
Dept. of Electron. Comput. Eng., Univ. of Limerick, Limerick
Abstract :
IEEE 1500 test wrappers that enable higher test bandwidth capability, system bus connectivity and efficient test vector organization are presented. Embedded core wrappers and test vectors that seamlessly work with ASIC and FPGA design flows are illustrated. Implementation and test-chip design show the positive impact on test time with potential for minimal wiring and logic overhead savings.
Keywords :
application specific integrated circuits; field programmable gate arrays; system-on-chip; wrapping; ASIC; FPGA design flows; embedded core wrappers; high test bandwidth capability; logic overhead savings; optimal IEEE 1500 core wrapper design; reduced test time; system bus connectivity; test vector organization; test-chip design; ASIC; Core Test; DFT; FPGA Prototyping; IEEE 1500; SoC Test;
Conference_Titel :
Signals and Systems Conference, 208. (ISSC 2008). IET Irish
Conference_Location :
Galway
Print_ISBN :
978-0-86341-931-7
