Performance optimization algorithm for DDR interface

While the demand for memory capacity and performance continues to increase, current DDR memory implementations start to encounter limitations. At high data rates of 533MT/s and above, it becomes increasingly difficult to support different combinations of DDR raw card types on the same platform due to the possible variations in load. This paper outlines a method of maximizing the DDR bus performance by utilizing hardware circuitry in the memory controller in connection with software algorithms to adjust the DDR transaction timing relationships based on the populated memory configuration. The algorithm also compensate for the effects of ageing over the lifetime of the part. The techniques used in this work are related to DDR-2 but could also be applicable to DDR-3 and future technologies.