DocumentCode :
484803
Title :
A hardware implementation of a run length encoding compression algorithm with parallel inputs
Author :
Trein, J. ; Schwarzbacher, A.T. ; Hoppe, B. ; Noffz, K.-H.
Author_Institution :
Sch. of Electron. & Commun. Eng., Dublin Inst. of Technol., Dublin
fYear :
2008
fDate :
18-19 June 2008
Firstpage :
337
Lastpage :
342
Abstract :
Run length encoding can be found in numerous applications such as data transfer or image storing (Sayood, 2002). It is a well known, easy and efficient compression method based on the assumption of long data sequences without the change of content. These sequences can be described by their position and length of appearance. Implementations using dedicated logic are optimised for parallel data processing. Here, images are transferred in blocks of multiple pixels in parallel. A compression of these streams into a run length code requires an encoder with a parallel input. This run length encoder has to compress the sequence at a minimum of clock cycles to avoid long inhibit intervals at the input. This paper describes a hardware algorithm performing a high performance run length encoding for binary images using a parallel input.
Keywords :
data compression; image coding; image sequences; runlength codes; binary images; hardware algorithm; hardware implementation; image compression; image sequences; parallel data processing; run length encoding compression algorithm; ASIC; DSP; FPGA; RLE; data compression; parallel image processing;
fLanguage :
English
Publisher :
iet
Conference_Titel :
Signals and Systems Conference, 208. (ISSC 2008). IET Irish
Conference_Location :
Galway
ISSN :
0537-9989
Print_ISBN :
978-0-86341-931-7
Type :
conf
Filename :
4780976
Link To Document :
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