DocumentCode
484808
Title
Proposed architecture of configurable, adaptable SoC
Author
Kadlec, Josef ; Danek, M. ; Kohout, L.
Author_Institution
Dept. of Signal Process., Inst. of Inf. Theor. & Autom., Prague
fYear
2008
fDate
18-19 June 2008
Firstpage
368
Lastpage
373
Abstract
To study the concept of Self Adaptive Networked computing Elements (SANE) we developed a configurable platform based on the Xilinx EDK and Xilinx System Generator tools. The platform is built around a MicroBlaze CPU with a set of standard peripherals such as DDR RAM controller and RS232 interface - denoted as "Master", extended with a set of several "reprogrammable Accelerators" connected to the MicroBlaze "Master" via fast simplex links (FSL).
Keywords
DRAM chips; peripheral interfaces; reconfigurable architectures; system-on-chip; DDR RAM controller; MicroBlaze CPU; RS232 interface; Xilinx EDK; Xilinx system generator tools; adaptable SoC; configurable architecure; fast simplex links; reprogrammable accelerators; self adaptive networked computing elements; standard peripherals; MicroBlaze; PicoBlaze; floating point accelerators; runtime reconfiguration;
fLanguage
English
Publisher
iet
Conference_Titel
Signals and Systems Conference, 208. (ISSC 2008). IET Irish
Conference_Location
Galway
ISSN
0537-9989
Print_ISBN
978-0-86341-931-7
Type
conf
Filename
4780981
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